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AccessRunner ADSL Modem Device Set for PCI Applications
Controller-less, Scalable, Discrete Multitone-based, G.dmt- and G.litecompliant, ADSL Modem Device Set for PCI Applications
Conexant's AccessRunner ADSL modem device set is compliant with the full-rate ANSI T1.413 Issue 2 and ITU G.dmt (G.992.1) ADSL standards, and with the splitterless ITU G.lite (G.992.2) specification. This rate-adaptive solution is designed for controllerless PCI desktop applications and supports downstream data rates of up to 8 Mbps and upstream data rates of up to 1 Mbps. The device set takes advantage of the processing power available with most new computers by eliminating the need for a separate microcontroller, resulting in a cost-effective solution suitable for both G.dmt and G.lite applications. Host-based software provides support for current industry standards for PPP over AAL5 over ATM over ADSL and RFC 1483 for Windows 98 and Windows 2000. The device set, as shown in Figure 1, consists of four chips: * * * * PCI bus interface (AccessRunner P46 in a 176-pin TQFP) DMT-based data pump (AccessRunner 11627 in a 176-pin TQFP) Analog front end (AccessRunner 20431 in a 32-pin TQFP) Line driver (AccessRunner 20441 in a 16-pin SSOP or 32-pin TQFP)
Features
* Complete controller-less PCI ADSL solution * Compliant with ADSL standards - Full-rate ANSI T1.413 Issue 2 and ITU G.dmt (G.992.1) standards - Splitterless ITU G.lite (G.992.2) specification * DMT modulation and demodulation * Full-rate adaptive modem - Maximum downstream rate of 8 Mbps - Maximum upstream rate of 1 Mbps * Supports splitterless ADSL implementation * WAN mode support: PPP over AAL5/ATM over ADSL via Windows 98/2000 * LAN mode support: RFC 1483 via Windows 98/2000 * Compliant with PCI Local Bus Specification, Revision 2.2 * Compliant with PCI Bus Power Management Interface Specification, Version 1.0 * Tone detection for low power mode
D20431 AFE Features
PCI Bus
HostBased ADSL Controller Software
P46 PCI Bus Interface 176-pin TQFP
11627 ADSL DMT Data Pump 176-pin TQFP
20431 Analog Front End 32-pin TQFP
20441 Line Driver 16-pin TSSOP
Telephone Line
Figure 1. AccessRunner ADSL Modem for PCI Applications
* Receive signal path includes: - Integrated hybrid receiver circuit with programmable gain - High pass filtering and 27dB of Automatic Gain Control (AGC) to improve signal-to-echo ratio - 14-bit ADC * Transmit signal path includes: - 30dB of AGC for transmit power control - Low pass filtering to suppress noise in the receive band - 14-bit DAC Independent digital serial data and control * interfaces Low power tone detection mode. *
Data Sheet (Preliminary)
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Doc. No.100394B October 19, 1999
AccessRunner
Controller-less ADSL Modem Device Set for PCI Applications
ADSL (Asymmetric Digital Subscriber Line) is a transmission technology used to carry user data over a single twisted pair line from the Central Office to the customer premises. The downstream (Central Office to Customer Premises) direction typically supports a much higher data rate than the upstream or return (Customer Premises to Central Office) channel. This asymmetric nature lends itself to applications like remote LAN access, Internet access, and video delivery. The downstream data rates can go up to 8 Mbps. The upstream data rates can go up to 1 Mbps. Actual data rates depend on the transceiver implementation, loop length, impairments, and transmitted power. The Conexant ADSL Modem Device Set for PCI Applications is based upon a scalable architecture. This architecture will enable the device set to support an emerging set of ADSL specifications called G.lite. G.lite is expected to make it possible for telcos to deploy consumer-oriented, "always on" 1.5 Mbps Internet access services without the need for splitter equipment or wiring changes at the customer premises.
D20441 Line Driver Features
* Differential input and output line driver * Thermal shutdown capability * Line impedance matching during powerdown * Fixed differential gain
11627 ADSL DMT Data Pump Features
* Low power (0.5W) consumption * DSP-based programmable ADSL data pump * No external Interleave RAM, 16 Kbytes built-in * Single 3.3V 5% power supply * Echo cancellation * Digital interface and rate buffering * ADSL framing * Forward Error Correction (FEC) encoding and decoding and interleaving * Constellation encoding/decoding * IFFT modulation and FFT demodulation * Transmit and receive signal digital filtering * Time domain equalization * Frequency domain equalization * Clock recovery * CRC and scrambling * Digital interface framing * ATM mode * Bit-synchronous mode
Ordering Information
Product AccessRunner P46 PCI Bus Interface AccessRunner 11627 ADSL Discrete Multitone (DMT) Data Pump AccessRunner 20431 Analog Front End AccessRunner 20441 Line Driver Package 176-pin TQFP 176-pin TQFP 32-pin TQFP 16-pin SSOP 32-pin TQFP Device Number P46 11627 20431 20441-12 20441-11
Revision History
Revision A B Date 07/09/99 10/19/99 Comments Initial release Defined dash numbers and updated figures for 20441 line driver, changed document number from DSL015, A
Information provided by Conexant Systems, Inc. is believed to be accurate and reliable. However, no responsibility is assumed by Conexant for its use, nor any infringement of patents or other rights of third parties which may result from its use. No license is granted by implication or otherwise under any patent rights of Conexant other than for circuitry embodied in Conexant products. Conexant reserves the right to change circuitry at any time without notice. This document is subject to change without notice. Conexant products are not designed or intended for use in life support appliances, devices, or systems where malfunction of a Conexant product can reasonably be expected to result in personal injury or death. Conexant customers using or selling Conexant products for use in such applications do so at their own risk and agree to fully indemnify Conexant for any damages resulting from such improper use or sale. Conexant, "What's Next in Communications Technologies", AccessRunner, LANfinity, and the Conexant logo, are trademarks of Conexant Systems, Inc. Product names or services listed in this publication are for identification purposes only, and may be trademarks or registered trademarks of their respective companies. All other marks mentioned herein are the property of their respective owners. (c)1999, Conexant Systems, Inc. All Rights Reserved
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Controller-less ADSL Modem Device Set for PCI Applications
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Detailed Description
P46 PCI Bus Interface The P46 PCI bus interface is the bridge device between the 11627 ADSL DMT data pump and the host computer. It provides the control, interface, and data manipulation for the 11627 data pump, the 20431 AFE, the 20441 line driver, and hybrid circuitry. It is compliant with the PCI Local Bus Specification, Revision 2.2 and PCI Bus Power Management Interface Specification, Version 1.0. 20431 Analog Front End The 20431 AFE is designed for use in full-rate and G.lite (G.992.2) ADSL modems. The ADSL AFE interfaces with the transmit line driver (20441) and the hybrid receive circuitry on the analog side, and with the ADSL DMT data pump (11627) on the digital side. The receive section filters out the unwanted echo and boosts the wanted signal before performing an A/D conversion. The transmit section converts digital data to analog signals and performs a smoothing operation before presenting the signals to the line driver. The 20431 is designed to operate from a 3.3V supply (nominal), assuming that it is regulated within 5%. The maximum allowable supply voltage is 3.6V.
11627 ADSL DMT Data Pump The 11627 DMT data pump is a T1.413 Issue 2 and G.992.1 compliant custom digital signal processing (DSP) chip built specifically for DMT ADSL transmission for use in ADSL modems. Brief descriptions of each functional block within the data pump are provided in the following sections; refer to Figure 2. ATM Transmission Convergence (TC) In the transmit direction, this block is in charge of embedding ATM cells into the serial data streams being fed into the digital interface. In the receive direction, this block extracts the ATM cell boundaries from the serial data streams coming from the digital interface. To reduce traffic on the PCI bus, the TC block performs idle cell insertion in the transmit direction and idle cell deletion and header error correction in the receive direction.
Digital Interface (DI) DI Transmit Block
AM EncoderDecoder
FFT
AFE Interface
ATM TC
Bit Parser and QAM Encoder
IFFT
Transmit Filter
DAC Intf EC AFE (20431)
PCI Controller (P46)
DI Receive Block
QAM Decoder and Bit Parser
FEQ
FFT
Time Domain Equalizer
ADC Intf
Microcontroller Interface
DMT Data Pump (11627)
DSL015002
Figure 2. AccessRunner 11627 DMT Data Pump Functional Block Diagram
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Controller-less ADSL Modem Device Set for PCI Applications
Digital Interface (DI) The DI Transmit Block performs the following functions: transmit data multiplexing and buffering, fast and interleave data stream framing, transmit data synchronization control, eoc/aoc insertion, CRC encoding, scrambling, FEC encoding, and data interleaving. The DI Receive Block performs the following functions: data de-interleaving, FEC decoding, descrambling, CRC check, receive data synchronization and receive clock generation, demultiplexing and buffering of receive data and receive eoc/aoc. QAM Encoder/Decoder The QAM Encoder/Decoder performs the following functions: constellation encoding, clock recovery, receive gain compensation, frequency domain equalization (FEQ), slicing, and constellation decoding. The block also performs other functions like frequency domain signal processing, signal power, error power averaging and computations related to frequency domain training. FFT The FFT performs IFFT for modulation of the transmit symbol, and FFT for demodulation of the receive symbol.
Analog Front End (AFE) Interface The AFE Interface performs the following functions: transmit signal filtering, time domain equalization, and time domain signal power averaging, and echo cancellation (EC). Microcontroller Interface The microcontroller interface enables the host computer via the PCI controller to set parameters to control DSP sequencing and to read/write coefficients or data. 20441 Line Driver The 20441 line driver is designed for use in full-rate and G.lite (G.992.2) ADSL modems. It is optimized for ideal ADSL performance providing low noise, high bandwidth, and superior linearity. The 20441 line driver transmits a DMT modulated signal in the 25 - 132 kHz band. It operates from a single 5V TBD% supply, refer to Figure 3. The driver is optimized for ADSL performance: it has a very low noise figure, high bandwidth and good linearity.
248.4 OUTP_DRV
INP_DRV
+
400
+
INM_DRV
+
248.4 OUTM_DRV
RBIAS
Current Control Block
(
Line Driver ) (20441)
DSL015_003
Figure 3. AccessRunner 20441 Line Driver 4
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Controller-less ADSL Modem Device Set for PCI Applications
AccessRunner
P46 PCI Bus Interface Device Hardware Pins and Signals
The pin assignments for the P46 are shown in Figure 4 and listed in Table 1. The signals are defined in Table 2.
176 175 174 173 172 171 170 169 168 167 166 165 164 163 162 161 160 159 158 157 156 155 154 153 152 151 150 149 148 147 146 145 144 143 142 141 140 139 138 137 136 135 134 133
GND SCANEN SCANMODE PCI_VPCIEN# PCI_VAUXEN# NC NC NC NC NC NC VDD PCI_VPCIDET PCI_VAUXDET GND DP_TCLKLS0 DP_TXSOC0 DP_TDATLS0 DP_RCLKAS0 VDD DP_RXSOC0 DP_RDATAS0 GND AFE_SCLK AFE_STB AFE_CTRLIN AFE_CTRLOUT AFE_WAKEUP DP_IRQ#[1] DP_IRQ#[0] VDD DP_A[9] DP_A[8] GND DP_A[7] DP_A[6] DP_A[5] DP_A[4] DP_A[3] DP_A[2] DP_A[1] DP_A[0] DP_WR# VDD
VDD GPIN0 GPIN1 GPIO[0] GPIO[1] GPIO[2] GND GPIO[3] GPIO[4] VDD GPIO[5] GPIO[6] GPIO[7] GPIO[8] GND TDI_GPIO[9] TMS_GPIO[10] VDD REFCLK TRSTN_GPIO[11] PCI_VPCIPREFER VDD TCK TDO GND PCI_INTA# PCI_RST# VDD PCI_CLK GND PCI_GNT# PCI_REQ# PCI_AD[31] VDD PCI_AD[30] PCI_AD[29] GND PCI_AD[28] PCI_AD[27] VGG1 VDD PCI_AD[26] PCI_AD[25] GND
1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 32 33 34 35 36 37 38 39 40 41 42 43 44
132 131 130 129 128 127 126 125 124 123 122 121 120 119 118 117 116 115 114 113 112 111 110 109 108 107 106 105 104 103 102 101 100 99 98 97 96 95 94 93 92 91 90 89
GND DP_RD# DP_CS# DP_D[15] DP_D[14] DP_D[13] VDD DP_D[12] DP_D[11] GND DP_D[10] DP_D[9] DP_D[8] DP_D[7] DP_D[6] VDD DP_D[5] DP_D[4] GND DP_D[3] DP_D[2] GND DP_D[1] DP_D[0] VDD EEPROM_CS EEPROM_CLK EEPROM_DOUT EEPROM_DIN VGG2 PCI_PME VDD PCI_AD[0] PCI_AD[1] GND PCI_AD[2] PCI_AD[3] VDD PCI_AD[4] PCI_AD[5] GND PCI_AD[6] PCI_AD[7] VDD
VDD PCI_AD[24] PCI_CBE#[3] PCI_IDSEL GND PCI_AD[23] PCI_AD[22] VDD PCI_AD[21] PCI_AD[20] GND PCI_AD[19] PCI_AD[18] VDD PCI_AD[17] PCI_AD[16] GND PCI_AD[15] PCI_CBE#[2] VDD PCI_FRAME# PCI_IRDY# GND PCI_TRDY# PCI_DEVSEL# PCI_STOP# PCI_PERR# VDD PCI_SERR# PCI_PAR PCI_CBE#[1] GND PCI_AD[14] PCI_AD[13] VDD PCI_AD[12] PCI_AD[11] GND PCI_AD[10] PCI_AD[9] VDD PCI_AD[8] PCI_CBE#[0] GND
45 46 47 48 49 50 51 52 53 54 55 56 57 58 59 60 61 62 63 64 65 66 67 68 69 70 71 72 73 74 75 76 77 78 79 80 81 82 83 84 85 86 87 88
DSL015004
Figure 4. P46 Pinout Diagram
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Controller-less ADSL Modem Device Set for PCI Applications
Table 1. P46 Pin Designations by Number
Pin No. 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 32 33 34 35 36 37 38 39 40 41 42 43 44 Signal VDD GPIN0 GPIN1 GPIO[0] GPIO[1] GPIO[2] GND GPIO[3] GPIO[4] VDD GPIO[5] GPIO[6] GPIO[7] GPIO[8] GND TDI_GPIO[9] TMS_GPIO[10] VDD REFCLK TRSTN_GPIO[11] PCI_VPCIPREFER VDD TCK TDO GND PCI_INTA# PCI_RST# VDD PCI_CLK GND PCI_GNT# PCI_REQ# PCI_AD[31] VDD PCI_AD[30] PCI_AD[29] GND PCI_AD[28] PCI_AD[27] VGG1 VDD PCI_AD[26] PCI_AD[25] GND Pin No. 45 46 47 48 49 50 51 52 53 54 55 56 57 58 59 60 61 62 63 64 65 66 67 68 69 70 71 72 73 74 75 76 77 78 79 80 81 82 83 84 85 86 87 88 Signal VDD PCI_AD[24] PCI_CBE#[3] PCI_IDSEL GND PCI_AD[23] PCI_AD[22] VDD PCI_AD[21] PCI_AD[20] GND PCI_AD[19] PCI_AD[18] VDD PCI_AD[17] PCI_AD[16] GND PCI_AD[15] PCI_CBE#[2] VDD PCI_FRAME# PCI_IRDY# GND PCI_TRDY# PCI_DEVSEL# PCI_STOP# PCI_PERR# VDD PCI_SERR# PCI_PAR PCI_CBE#[1] GND PCI_AD[14] PCI_AD[13] VDD PCI_AD[12] PCI_AD[11] GND PCI_AD[10] PCI_AD[9] VDD PCI_AD[8] PCI_CBE#[0] GND Pin No. 89 90 91 92 93 94 95 96 97 98 99 100 101 102 103 104 105 106 107 108 109 110 111 112 113 114 115 116 117 118 119 120 121 122 123 124 125 126 127 128 129 130 131 132 Signal VDD PCI_AD[7] PCI_AD[6] GND PCI_AD[5] PCI_AD[4] VDD PCI_AD[3] PCI_AD[2] GND PCI_AD[1] PCI_AD[0] VDD PCI_PME VGG2 EEPROM_DIN EEPROM_DOUT EEPROM_CLK EEPROM_CS VDD DP_D[0] DP_D[1] GND DP_D[2] DP_D[3] GND DP_D[4] DP_D[5] VDD DP_D[6] DP_D[7] DP_D[8] DP_D[9] DP_D[10] GND DP_D[11] DP_D[12] VDD DP_D[13] DP_D[14] DP_D[15] DP_CS# DP_RD# GND Pin No. 133 134 135 136 137 138 139 140 141 142 143 144 145 146 147 148 149 150 151 152 153 154 155 156 157 158 159 160 161 162 163 164 165 166 167 168 169 170 171 172 173 174 175 176 Signal VDD DP_WR# DP_A[0] DP_A[1] DP_A[2] DP_A[3] DP_A[4] DP_A[5] DP_A[6] DP_A[7] GND DP_A[8] DP_A[9] VDD DP_IRQ#[0] DP_IRQ#[1] AFE_WAKEUP AFE_CTRLOUT AFE_CTRLIN AFE_STB AFE_SCLK GND DP_RDATAS0 DP_RXSOC0 VDD DP_RCLKAS0 DP_TDATLS0 DP_TXSOC0 DP_TCLKLS0 GND PCI_VAUXDET PCI_VPCIDET VDD NC NC NC NC NC NC PCI_VAUXEN# PCI_VPCIEN# SCANMODE SCANEN GND
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Controller-less ADSL Modem Device Set for PCI Applications
AccessRunner
Table 2. P46 Pin Signals by Group
Pin Name PCI INTERFACE PCI_AD[31:0] PCI_CBE#[3:0] PCI_FRAME# PCI_IRDY# PCI_TRDY# PCI_PAR PCI_STOP# PCI_DEVSEL# PCI_IDSEL PCI_PERR# PCI_SERR# PCI_REQ# PCI_GNT# PCI_CLK PCI_RST# PCI_INTA# PCI_PME I/O I/O I/O I/O I/O I/O I/O I/O I I/O O O I I I (S) O O Address/Data Command/Byte Enables Frame Initiator Ready Target Ready Parity (Even) Target Stop Target Response Device Select Unique Select for Configuration Parity Error System Error Master Request Grant PCI clock Reset Interrupt A PCI Power Management Event Signal I/O
1
Description
ADSL DMT DATA PUMP (11627) SERIAL CHANNEL INTERFACE DP_RDATAS0 DP_RXSOC0 DP_RCLKAS0 DP_TDATLS0 DP_TXSOC0 DP_TCLKLS0 I I I O O I Receive AS0/ATM0 Serial Data Receive ATM0 Start of Cell Receive AS0/ATM0 Data Clock Transmit LS0/ATM0 Serial Data Transmit ATM0 Start of Cell Transmit LS0/ATM0 Data Clock
ADSL DMT DATA PUMP (11627) MICRO INTERFACE DP_WR# DP_RD# DP_D[15:0] DP_A[9:0] DP_CS# DP_IRQ#[1:0] ANALOG FRONT END INTERFACE AFE_SCLK AFE_STB AFE_CTRLIN AFE_CTRLOUT I O O I Serial AFE Clock AFE Strobe Serial Data Sent to AFE Serial Data Received from AFE O O I/O (PU) O O I (PU,S) Data Pump Device Write Enable Data Pump Device Read Enable Data Pump Data Lines Data Pump Address Lines Data Pump Chip Select Data Pump Interrupt Request Lines
1
PD PU S
Resistive pull-down Resistive pull-up Schmitt
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Pin Name AFE_WAKEUP SERIAL EEPROM EEPROM_CS EEPROM_CLK EEPROM_DIN EEPROM_DOUT PCI POWER MANAGEMENT PCI_VAUXDET PCI_VPCIDET PCI_VAUXEN# PCI_VPCIEN# PCI_VPCIPREFER MISCELLANEOUS GPIO[1:0] GPIO[2:5], GPIO[8] GPIO[6] GPIO[7] TDI_GPIO[9] I/O (PU,S) I/O (PU) I/O I/O I/O (PU) I (PD,S) I (PD,S) O O I Vaux Detect Vpci Detect Vaux Enable Vpci Enable O O I O I/O
1
Controller-less ADSL Modem Device Set for PCI Applications
Description DSL Power Management Wakeup Signal from AFE
I (S)
EEPROM Chip Select EEPROM Clock EEPROM Data Input EEPROM Data Output
This pin is used to determine whether Vpci or Vaux is the preferred power supply. 1=Vpci preferred, 0=Vaux preferred
General Purpose Schmitt Input/Output General Purpose Input/Output General Purpose Input/Output (also used for active low reset) General Purpose Input/Output (also used for active high reset) JTAG test data input OR general purpose input/output. Function of this pin is dependant upon value of JTAGEN bit. When operating in JTAG mode this signal contains serial data that is shifted in on the rising edge of TCK. JTAG test mode select OR general purpose input/output. Function of this pin is dependant upon value of JTAGEN bit. When operating in JTAG mode this siganl controls the operation of the TAP controller.
TMS_GPIO[10]
I/O (PU)
TRSTN_GPIO[11]
I/O (PU)
JTAG reset OR general purpose input/output. Function of this pin is dependant upon value of JTAGEN bit. When operating in JTAG mode, a high to low transition on this signal forces the TAP controller into a logic reset state.
TCK TDO GPIN0 GPIN1 SCANEN SCANMODE REFCLK POWER AND GROUND VDD GND VGG1 VGG2
I O I (S) I (PU,S) I (PD) I (PD) I
JTAG clock. JTAG data output. This pin generates serial data that is shifted out on the falling edge of TCK.. General purpose schmitt input (modem ring detect) General purpose schmitt input (modem offhook) Scan chain enable. Used to shift data in and out of the scan chain. Scan mode enable pin. When tied high it will put the device into scan test mode. 35.328 MHz reference clock used to create the internal 53 MHz system clock
3.3V Power Ground I/O Clamp Power Supply for PCI Signalling Environment (connect to VIO pin of PCI Bus) I/O Clamp Power Supply for Backend (connect to 3.3 volt supply)
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Controller-less ADSL Modem Device Set for PCI Applications
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11627 ADSL DMT Data Pump Hardware Pins and Signals
The pin assignments for the 11627 are shown in Figure 5 and listed in Table 3. The signals are defined in Table 4.
VDD VDDcore
VDDcore GND
VDDcore GND
169 168
176
175 174
173 172
171 170
167 166
165 164
163 162
161 160
159 158
157 156
155 154
153 152
151 150
GND DAC_CLK FILTER_CLK T_FAST_BYTE# T_INTER_BYTE# R_CLK_AS1 NC NTR GND VDD R_CLK_AS0 NC T_CLK_LS1 T_DAT_LS1 T_CLK_LS0 T_DAT_LS0 BIT_CLOCK GND GND GND TXSOC0 TLXCK_EN TXSOC1 AFE_STR# VDDcore VDDcore VDD GND NTRCTL DMCK_ALT R_INTER_SUPER# R_INTER_DATA R_FAST_SUPER# R_FAST_FRAME# GND VDD R_NCO_LS0 R_NCO_LS1 R_NCO_AS0 R_NCO_AS1 R_DAT_AS0 R_DAT_AS1 NC NC
1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 32 33 34 35 36 37 38 39 40 41 42 43 44
149 148
147 146
145 144
143 142
141 140
139 138
137 136
135 134
133
VDDcore GND
RX[15] RX[14]
RX[13] RX[12]
RX[11] RX[10]
TX[15] TX[14]
TX[13] TX[12]
TX[11] TX[10]
RX[9] RX[8]
RX[7] RX[6]
RX[5] RX[4]
RX[3] RX[2]
TX[9] TX[8]
TX[7] TX[6]
TX[5] TX[4]
TX[3] TX[2]
TX[1] TX[0]
VDD GND
VDD GND
GND GND
132 131 130 129 128 127 126 125 124 123 122 121 120 119 118 117 116 115 114 113 112 111 110 109 108 107 106 105 104 103 102 101 100 99 98 97 96 95 94 93 92 91 90 89
VDD GND RX[1] RX[0] ADC_CLK D[0] D[1] D[2] D[3] D[4] VDD GND D[5] D[6] D[7] D[8] D[9] D[10] D[11] D[12] D[13] D[14] VDD VDDcore VDDcore GND GND GND D[15] VGG A[0] A[1] A[2] A[3] A[4] A[5] A[6] A[7] A[8] VDDcore GND A[9] WR# VDD
45
46 47
48 49
50 51
52 53
54 55
56 57
58 59
60 61
80 81
62 63
64 65
66 67
68 69
70 71
72 73
74 75
76 77
78 79
R_DAT_LS0 R_CLK_LS1
R_DAT_LS1 NC
RXSOC0
RXSOC1 R_CLK_LS0
VCXO_CTRL MON_DONE
GND GND
VDD NC
IRQ[1]# IRQ[0]#
82 83
NC VDDcore
VDDcore VDDcore
VDDcore VDDcore
VDD MON_OUT
CLIP# RST#
MCLK VDD
GND NC
GND GND
GND GND
GND GND
NC LTR
NC NC
84 85
86 87 RD# CS#
MON_CLK PWR_DN
GND
88
DSL015_005
Figure 5. 11627 Pinout Diagram
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Controller-less ADSL Modem Device Set for PCI Applications
Table 3. 11627 Pin Designations by Number
Pin No. Signal 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 32 33 34 35 36 GND DAC_CLK FILTER_CLK T_FAST_BYTE# T_INTER_BYTE# R_CLK_AS1 NC NTR GND VDD R_CLK_AS0 NC T_CLK_LS1 T_DAT_LS1 T_CLK_LS0 T_DAT_LS0 BIT_CLOCK GND GND GND TXSOC0 TLXCK_EN TXSOC1 AFE_STR# VDDcore VDDcore VDD GND NTRCTL DMCK_ALT R_INTER_SUPER# R_INTER_DATA R_FAST_SUPER# R_FAST_FRAME# GND VDD Pin No. Signal 37 38 39 40 41 42 43 44 45 46 47 48 49 50 51 52 53 54 55 56 57 58 59 60 61 62 63 64 65 66 67 68 69 70 71 72 R_NCO_LS0 R_NCO_LS1 R_NCO_AS0 R_NCO_AS1 R_DAT_AS0 R_DAT_AS1 NC NC RXSOC0 RXSOC1 R_CLK_LS0 R_DAT_LS0 R_CLK_LS1 R_DAT_LS1 NC GND GND VDD NC NC NC NC VDDcore VDDcore VDDcore GND GND GND NC VCXO_CTRL MON_DONE MCLK VDD VDDcore VDDcore GND Pin No. Signal 73 74 75 76 77 78 79 80 81 82 83 84 85 86 87 88 89 90 91 92 93 94 95 96 97 98 99 100 101 102 103 104 105 106 107 108 GND GND GND VDD MON_OUT MON_CLK PWR_DN NC LTR IRQ[1]# IRQ[0]# CLIP# RST# RD# CS# GND VDD WR# A[9] GND VDDcore A[8] A[7] A[6] A[5] A[4] A[3] A[2] A[1] A[0] VGG D[15] GND GND GND VDDcore Pin No. Signal 109 110 111 112 113 114 115 116 117 118 119 120 121 122 123 124 125 126 127 128 129 130 131 132 133 134 135 136 137 138 139 140 141 142 143 144 VDDcore VDD D[14] D[13] D[12] D[11] D[10] D[9] D[8] D[7] D[6] D[5] GND VDD D[4] D[3] D[2] D[1] D[0] ADC_CLK RX[0] RX[1] GND VDD GND VDDcore RX[2] RX[3] RX[4] RX[5] GND VDDcore RX[6] RX[7] RX[8] RX[9] Pin No. Signal 145 146 147 148 149 150 151 152 153 154 155 156 157 158 159 160 161 162 163 164 165 166 167 168 169 170 171 172 173 174 175 176 RX[10] RX[11] RX[12] RX[13] RX[14] RX[15] GND GND GND VDDcore VDDcore VDD TX[0] TX[1] TX[2] TX[3] TX[4] TX[5] TX[6] TX[7] TX[8] TX[9] GND VDD TX[10] TX[11] TX[12] TX[13] TX[14] TX[15] GND VDD
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Controller-less ADSL Modem Device Set for PCI Applications
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Table 4. 11627 Pin Signals by Group
Pin Name I/O Description
AFE ANALOG-to-DIGITAL INTERFACE RX[15:0] I Receive Data Lines In the parallel mode of operation, data is clocked by the signal ADC_CLK using the full data bus. In the serial mode of operation, a strobe signal (AFE_STR#) from the AFE shall trigger the transfer of data over a programmable width serial bus. ADC_CLK CLIP# O O Receive Clock for Parallel Mode Clip Interrupt This signal is used for monitoring incoming data for saturation. Goes low for one clock (ADC_CLK) cycle whenever clipping is detected. AFE DIGITAL-to-ANALOG INTERFACE TX[15:0] O Transmit Data Lines In the parallel mode of operation, data is clocked by the signal DAC_CLK using the full data bus. In the serial mode of operation, a strobe signal (AFE_STR#) from the AFE shall trigger the transfer of data over a programmable width serial bus. DAC_CLK FILTER_CLK O O Transmit Clock for Parallel Mode AFE Filter Clock This signal is used by the DAC interface block to strobe the external AFE filters. AFE_STR# DIGITAL INTERFACE (DI) TLXCK_EN T_CLK_LS0 T_CLK_LS1 T_DAT_LS0 T_DAT_LS1 R_CLK_LS0 R_CLK_LS1 R_DAT_LS0 R_DAT_LS1 R_CLK_AS0 R_CLK_AS1 R_DAT_AS0 R_DAT_AS1 R_NCO_LS0 R_NCO_LS1 R_NCO_AS0 R_NCO_AS1 BIT_CLOCK I I/O I/O I I I I O O I I O O O O O O O LSX Transmit Data Clock Generation Enable Transmit Data Clock (LS0) Transmit Data Clock (LS1) Transmit Data (LS0) Transmit Data (LS1) Receive Data Clock (LS0) Receive Data Clock (LS1) Receive Data (LS0) Receive Data (LS1) Receive Data Clock (AS0) Receive Data Clock (AS1) Receive Data (AS0) Receive Data (AS1) Receive LS0 NCO Output Receive LS1 NCO Output Receive AS0 NCO Output Receive AS1 NCO Output Serial Data Bit Clock Output Used to synchronize the serial input and output data bit streams, enables, and superframe qualifiers. T_FAST_BYTE# T_INTER_BYTE# R_FAST_FRAME# R_FAST_SUPER# O O O O Transmit Fast Data Bit Input Enable Transmit Interleaved Data Bit Input Enable Receive Fast Data Bit Output Frame Qualifier Receive Fast Data Bit Output Superframe Qualifier I AFE Strobe Signal
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Pin Name R_INTER_DATA I/O O Description
Controller-less ADSL Modem Device Set for PCI Applications
Receive Interleaved Data Bit Output Clocked at BIT_CLOCK rate.
R_INTER_SUPER# PCI CONTROLLER INTERFACE D[15:0]
O
Receive Interleaved Data Bit Output Superframe Qualifier
I/O
PCI Controller Interface Data Bus 16-bit input/output bus to send/receive data to/from PCI controller.
A[9:0]
I
PCI Controller Interface Address Bus 10-bit input bus to receive address from PCI controller.
WR# RD# CS# IRQ[1:0]# MISCELLANEOUS RST#
I I I O
Data Write Enable Data Read Enable Chip Select Programmable Interrupts
I
Global Chip Reset When low, puts chip into reset condition.
MCLK
I
High-speed Master Clock Connect to 35.328 MHz VCXO, which is 16 times the maximum Nyquist rate.
VXCO_CTRL
O
Oversampled VCXO analog control voltage
MON_OUT MON_CLK
O O
1-bit serial D/A output used for constellation monitoring Serial Monitor Clock Operates at 138 kHz.
MON_DONE DMCK_ALT LTR NTR NTRCTL TXSOC0 TXSOC1 RXSOC0 RXSOC1 PWR_DN POWER AND GROUND VDD VDDcore GND VGG
O I O I/O I I I O O I
New Symbol Constellation Qualifier External 2x Clock 8 kHz Local Timing Reference 8 kHz Network Timing Reference Network Timing Reference I/O Control TC0 Block Transmit Start of Cell. TC1 Block Transmit Start of Cell. TC0 Block Receive Start of Cell TC1 Block Receive Start of Cell Power Down Control Pin
3.3V Power (I/O) 2.5V Power (Core) Ground I/O Clamp Power Supply (connect to 5 volt supply for 5 volt tolerance)
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AccessRunner
20431 ADSL Analog Front End Hardware Pins and Signals
The pin assignments for the 20431 are shown in Figure 6 and defined in Table 5.
VREFM
VREFP
RBIAS
DVSS 27
32
31
30
29
28
26
INP_HYBR_RX INM_HYBR_RX INP_RX INM_RX AVDD AVSS OUTP_TX OUTM_TX
1 2 3 4 5 6 7 8
25
24 23 22 21 20 19 18 17
DVSS
NC
NC
VC
RX0 RX1 TX0 DVDD NC STROBE WAKEUP CTRL_OUT
10
11
12
13
14 DVSS
15 CTRL_STRB
CTRL_IN
AVDD
AVSS
CLKIN
NC
POR
16
9
DSL015_006
Figure 6. 20431 Pinout Diagram
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Table 5. 20431 Pin Signals by Group
Pin Name I/O Description Pin Number(s)
ADSL Digital Serial Data and Control Interface Signals CLKIN POR CTRL_STRB CTRL_IN CTRL_OUT WAKEUP STROBE TX0 RX1 RX0 I I I I O O O I O O Clock input (35.328MHz) Power On Reset Strobe for the control interface Digital input of the control interface Digital output of the control interface Digital output for tone detection mode Strobe for the data interface Digital transmit input Digital receive output Digital receive output 11 13 15 16 17 18 19 22 23 24
ADSL HYBRID CIRCUIT AND LINE DRIVER INTERFACE INP_HYBR_RX INM_HYBR_RX INP_RX INM_RX OUTP_TX OUTM_TX Overhead Signals VREFP VC VREFM RBIAS AVDD AVSS DVSS DVDD ----------------Analog reference voltage (2.5V) Analog reference voltage (1.5V) Analog reference voltage (0.5V) Analog current reference Analog supply Analog ground Digital ground Digital supply 29 30 31 32 5, 9 6, 10 14, 25, 27 21 I I I I O O Positive input of hybrid receiver circuit Negative input of hybrid receiver circuit Positive input of receive path Negative input of receive path Positive output of transmit path Negative output of transmit path 1 2 3 4 7 8
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AccessRunner
20441 ADSL Line Driver Hardware Pins and Signals
The pin assignments for the 20441 in both 16-pin TSSOP and 32-pin TQFP packages are shown in Figure 7 and defined in Table 6.
32 31 30 29 28 27 26 25
NC NC NC NC NC NC NC NC
NC INM_DRV NC RBIAS PWRDWN# AVDD OUTM_DRV AVSS
1 2 3 4 5 6 7 8
16 15 14 13 12 11 10 9
NC INP_DRV NC NC NC AVDD OUTP_DRV AVSS
NC INM_DRV NC RBIAS PWRDWN# AVDD OUTM_DRV AVSS
1 2 3 4 5 6 7 8
9 10 11 12 13 14 15 16
24 23 22 21 20 19 18 17
NC INP_DRV NC NC NC AVDD OUTP_DRV AVSS
16-pin TSSOP
NC NC NC NC NC NC NC NC
32-pin TQFP
DSL015_007
Figure 7. 20441 Pinout Diagrams
Table 6. 20441 Pin Signals by Group
Pin Name I/O Description Comment Pin Number(s) 16 SSOP INP_DRV INM_DRV OUTP_DRV I I O Positive transmit output of the AFE Negative transmit output of the AFE Positive output of the line driver Analog input Analog input Analog output Imax=244mA (16 SSOP) Imax=280mA (32 SSOP) Analog output Imax=244mA (16 SSOP) Imax=280mA (32 TQFP) Digital input (3V level) Tied to 125k resistor (+1%) 15 2 10 32 TQFP 23 2 18
OUTM_DRV
O
Negative output of the line driver
7
7
PWRDWN# RBIAS POWER AVDD AVSS
I I
Power down control (0 = power down) Current setting external resistor
5 4
5 4
Analog supply (+5V) Analog ground
Imax=273.2mA (16 SSOP) Imax=309.2mA (32 TQFP) Imax=273.2mA (16 SSOP) Imax=309.2mA (32 TQFP)
6, 11 8, 9
6, 19 8, 17
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Controller-less ADSL Modem Device Set for PCI Applications
Electrical and Environmental Specifications
AccessRunner P46 PCI Bus Interface Device
Table 7. DC Characteristics
Parameter Power Supply I/O Clamp Power Supply Input Low Voltage Input High Voltage Output Low Voltage Output High Voltage I/O Clamp Power Supply Input Low Voltage Input High Voltage Output Low Voltage Output Low Voltage Output High Voltage Input Low Voltage Input High Voltage Output Low Voltage Output High Voltage Pull-Up Resistance Pull-Down Resistance Symbol VDD VIO VIL VIH VOL VOH VIO VIL VIH VOL VOL VOH VIL VIH VOL VOH Rpu Rpd 2.4 TTL Signal Levels -0.5 2.0 2.4 Misc 50 50 200 200 Kohm Kohm 0.8 Vdd + 0.5 0.4 VDC VDC VDC VDC Minimum Power 3.0 VDD -0.5 0.5 * Vdd 0.9 * Vdd VDD -0.5 2.0 5.25 0.8 Vdd + 0.5 0.55 0.55 3.6 3.6 0.3 * Vdd Vdd + 0.5 0.1 * Vdd VDC VDC VDC VDC VDC VDC VDC VDC VDC VDC VDC VDC PCI Signal/Power Levels - 3V signalling environment Maximum Units Conditions
Iout = -500 mA Iout = 1500mA
PCI Signal/Power Levels - 5V signaling environment
Iout = 3mA, signals without pullups Iout = 6mA, signals with pullups Iout = -2mA
16
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AccessRunner 11627 ADSL DMT Data Pump
Table 8. Recommended Operating Conditions
Parameter Power Supply (I/O) Power Supply (Core) Ambient Operating Temperature Humidity Symbol VDD VDDcore TA Min 3.135 2.375 -40 Typ 3.3 2.5 Max 3.465 2.625 +85 90 Units Volts Volts C %
Table 9. Absolute Maximum Ratings
Parameter Power Supply Voltage on any Signal Pin Ambient Operating Temperature Storage Temperature Junction Temperature Soldering Temperature Vapor Phase Soldering Air Flow TA TS TJ TSOL TVSOL 0 Symbol VDD GND-0.3 -55 -65 Min Typ Max 3.6 VDD+0.3 +125 +150 +150 +260 +220 Units Volts Volts C C C C C l.f.p.m
Table 10. DC Characteristics
Parameter Digital Inputs Input High Voltage Input Low Voltage Input Leakage Current Input Capacitance Digital Outputs Output High Voltage Output Low Voltage Tri-State Output Leakage Output Capacitance Digital Bi-directionals Tri-State Output Leakage Input/Output Capacitance ILK CINOUT -10 3.9 10 A pF VOH VOL ILK COUT 0.9*VDD GND 10 3.1 VDD 0.1*VDD 10 Volts Volts A pF VIH VIL IIL/IIH CIN 0.9*VDD GND -10 2.9 VDD 0.1*VDD 10 Volts Volts A pF Symbol Min Typ Max Units
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AccessRunner
Controller-less ADSL Modem Device Set for PCI Applications
AccessRunner 20431 AFE
Table 11. Recommended Operating Conditions
Parameter Power supply Operating junction temperature Operating ambient temperature Min 3.135 -40 -40 Typ 3.3 Max 3.465 +100 +85 Units V
o
C C
o
Table 12. Absolute Maximum Ratings
Parameter Power supply Analog input voltage Digital input voltage Input current per Pin Output current per Pin Short circuit duration, to GND or Vdd Ambient temperature (power applied) Storage temperature -55 -65 Min -0.35 -0.35 -0.35 -10 -50 Max 3.6 Vdd+0.35 Vdd+0.35 10 50 1 +125 +150 Units V V V mA mA sec
o
C C
o
Table 13. Power Consumption
Parameter Analog Digital Min Typ 40.5 25 Max Units mA mA
Table 14. Digital Characteristics
Parameter High level input voltage Low level input voltage High level output voltage Low level output voltage Input leakage current Output leakage current Min 0.65*VDD -0.35 0.85*VDD 0 -10 -10 Max VDD+0.35 0.25*VDD VDD 0.1*VDD 10 10 Units V V V V A A
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AccessRunner 20441 Line Driver
Table 15. Power Consumption
Parameter Line driver Min Typ 18 Max 24 Units mA
Table 16. Absolute Maximum Ratings
Parameter Power supply Analog input voltage Digital input voltage Input current per Pin Output current per Pin Short circuit duration, to GND or Vdd Ambient temperature (power applied) Storage temperature -55 -65 Min -0.35 -0.35 -0.35 -10 -50 Max 7 Vdd+0.35 Vdd+0.35 10 50 1 +125 +150 Units V V V mA mA Sec
o
C C
o
Table 17. Recommended Operating Conditions
Parameter Power supply Operating junction temperature Operating ambient temperature Min 4.75 -40 0 Typ 5 Max 5.25 +110 +70 Units V
o
C C
o
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AccessRunner
Controller-less ADSL Modem Device Set for PCI Applications
Package Dimensions
26.0 0.500
.20
0.500
26.0
.20
23.87
.10
24.00
.10
0.500
0.220 REF.
23.87
.10
Detail "A" 24.00 .10
12
R 0.15 TYP R 0.20 TYP
1.40
.05 0 -5 12 GAUGE PLANE SEATING PLANE 0.25
.05 MIN./.15 MAX. 1.00 REF. 0.30 REF. 0.60 + .15/ .10 DETAIL A
DSL015_008
Figure 8. 176-pin TQFP Package Dimensions 20
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D D1 D2
D
D1 D2
D1
e
b
Detail "A"
S Y M B O L A A1 A2 D D1 D2 L L1 e b c Coplanarity
Millimeters
Inches
MAX.
MIN.
MAX.
MIN.
D1
A
A2 c
1.6 MAX. 0.15 0.05 1.4 REF. 9.25 8.75 7.0 REF. 5.6 REF. 0.75 0.5 1.0 REF. 0.80 BSC 0.40 0.30 0.19 0.13 0.10 MAX.
0.0630 MAX. 0.0020 0.0059 0.0551 REF. 0.3445 0.3642 0.2756 REF. 0.2205 REF. 0.0197 0.0295 0.0394 REF. 0.0315 BSC 0.0118 0.0157 0.0051 0.0075 0.004 MAX.
Ref: 32-Pin TQFP (GP00-D262) A1 L L1 * Metric values (millimeters) should be used for PCB layout. English values (inches) are converted from metric values and may include round-off errors.
DETAIL A
DSL015_009
Figure 9. 32-pin TQFP Package Dimensions
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Controller-less ADSL Modem Device Set for PCI Applications
NOTES: 0.193 0.002 [WITHOUT FLASH] -A1. THERMAL HEATSINK/RF GROUND MATERIAL: OFHC COPPER 2. LEAD COPLANARITY IS 0.004 MAX. 3. L/F MATERIAL: COPPER 151, 0.0075 THICK 4. LEAD AND HEATSINK FINISH: 85Pb/15 -B5. FLASH IS 0.010 MAX. TOP VIEW 0.154 0.002 [WITHOUT FLASH] 5Sn
.0001 1 .0025 0.023 PIN 1 0.010 TYP. VIEW B SCALE 2:1
0.193 7 (TYP)
0.002
0.058 0.002 [MOLD]
R0.005 (TYP. 4X)
0.015 X 45
VIEW B 0 -7 TYP.
-C0.004 SEATING PLANE
VIEW A
0.194
0.002
0.000 0.004
O.008 TYP.
.174 END VIEW 0.024 0.002 MEASURED 0.0098 FROM SEATING PLANE
SIDE VIEW .110 FLASH (TYP)
0.236
0.004 .005 A B 0.008 MAX.
1
.066 BOTTOM VIEW 0.025 TYP.
UNLESS OTHERWISE SPECIFIED DIMENSIONS ARE IN INCHES TOERANCES ON: DECIMALS .XX .03 .XXX .002 ANGLES 0.30
VIEW A SCALE: 100:1 +0.004 0.010 -0.002 XXX M C 16 LEAD SSOP PACKAGE OUTLINE
DSL015_010
Figure 10. 16-pin SSOP Package Dimensions
22
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INSIDE BACK COVER NOTES
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